1. Field of the Invention
The present invention relates in general to a programmable logic array (referred to hereinafter as PLA) used as a logic circuit in a digital system, and more particularly to a reprogrammable PLA which can be readily manufactured and integrated.
2. Description of the Prior Art
All digital logic circuits can be designed in a table lockup manner with respect to input and output. For example, a read only memory (referred to hereinafter as ROM) and a PLA are mainly used in the design of the table lookup manner. The ROM allows only "1" and "0" as the table contents, whereas the PLA allows a don't care as well as "1" and "0" as the table contents. For example, a 2-input NAND gate function can be implemented by using the ROM and the PLA, as follows:
TABLE 1 ______________________________________ ROM PLA INPUT OUTPUT INPUT OUTPUT ______________________________________ 0 0 0 0 X 1 0 1 1 X 0 1 1 0 1 1 1 0 1 1 1 ______________________________________
As seen from the above table 1, the ROM must form the table with respect to all input cases because it does not allow a don't care as the input. Because allowing the don't care as the input, the PLA forms the table with contents of a number smaller than that of the ROM to perform the same function as that of the ROM. As a result, the PLA can readily be logic-designed in most cases by employing a hardware smaller in scale than that of the ROM. In this connection, the PLA is used as one of the logic integrated circuit (referred to hereinafter as IC) design manners. As semi-custom manners for designing the IC, there are a gate array manner, a standard cell manner and a programmable logic device (referred to hereinafter as PLD) manner. The design manner using the PLD provides the following advantages.
First, the system design requires no level lower than a logic gate level because control functions and data paths are directly compiled into a PLD description.
Second, in the case of using a reprogrammable PLD, an error can be corrected at a protype stage with no waste of cost.
Third, the design speed is very high.
Fourth, because signals are freely assigned to pins, it becomes simple to design a printed circuit board (PCB). The use of the reprogrammable PLD makes it easy to change or replace the existing functions.
Because of these advantages, the reprogrammable PLD has been deeply studied and has sold well on the market. The PLD includes a programmable read only memory (referred to hereinafter as PROM) cell, an erasable programmable read only memory (referred to hereinafter as EPROM) cell or an electrically erasable programmable read only memory (referred to hereinafter as EEPROM) cell to establish the reprogrammable operation. Alternatively, because of the above-mentioned design advantages, as a programmable device of the gate array type, a field programmable gate array (FPGA) device or an electrically configurable gate array (ECGA) device is mainly used for hardware emulation. However, such devices have a disadvantage in that they require a particular process in addition to a general CMOS process. Also, the reprogrammable PLD cannot have a capacity exceeding several thousand-gate class, because of limitations in structure and technique.